在用于格式4的arm模拟器中实现功能时的一个问题

a question in implementing a function in arm simulator for format 4

本文关键字：功能 一个 问题 实现 格式 用于 arm 模拟器      更新时间：2023-10-16

我的问题是关于在我的ARM拇指模拟函数中表示进位位和算术右移。如果操作码是ADC的二进制位值，那么我必须创建一个布尔变量吗？然后我将布尔变量加为1，如果不是，那么它是SBC？另外，如何在我的代码中表示ASR的逻辑？

格式4

操作码的格式4指令

case 2:           // format 4
op = (instr >> 6) & 0xF;
rd = instr & 7;
rs = (instr >> 3) & 7;
if (op == 0)
{
cout << " AND " << rd << "," << rs << endl;
Regs[rd] = Regs[rd] & Regs[rs];
}
else if (op == 1)
{
cout << " EOR " << rd << "," << rs << endl;
Regs[rd] = Regs[rd] ^ Regs[rs];
}
else if (op == 2)
{
cout << " LSL " << rd << "," << rs << endl;
Regs[rd] = Regs[rd] << Regs[rs];
}
else if (op == 3)
{
cout << " LSR " << rd << "," << rs << endl;
Regs[rd] = Regs[rd] >> Regs[rs];
}
**else if (op == 4)
{
cout << " ASR  " << rd << "," << rs << endl;
Regs[rd] = Regs[rd] >> Regs[rs];
}**
**else if (op == 5)
{
cout << " ADC " << rd << "," << rs << endl;
Regs[rd] = Regs[rd] & Regs[rs];
}
else if (op == 6)
{
cout << " SBC " << rd << "," << rs << endl;
Regs[rd] = Regs[rd] - Regs[rs];
}**
break;

我只给您一些工作代码供您思考。

void do_cflag ( unsigned int a, unsigned int b, unsigned int c )
{
unsigned int rc;
cpsr&=~CPSR_C;
rc=(a&0x7FFFFFFF)+(b&0x7FFFFFFF)+c; //carry in
rc = (rc>>31)+(a>>31)+(b>>31);  //carry out
if(rc&2) cpsr|=CPSR_C;
}    
void do_cflag_bit ( unsigned int x )
{
if(x) cpsr|=CPSR_C; else cpsr&=~CPSR_C;
}


//SUB(1)
if((inst&0xFE00)==0x1E00)
{
rd=(inst>>0)&7;
rn=(inst>>3)&7;
rb=(inst>>6)&7;
if(DISS) fprintf(stderr,"subs r%u,r%u,#0x%Xn",rd,rn,rb);
ra=read_register(rn);
rc=ra-rb;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
do_cflag(ra,~rb,1);
do_vflag(ra,~rb,1);
return(0);
}
//SBC
if((inst&0xFFC0)==0x4180)
{
rd=(inst>>0)&0x7;
rm=(inst>>3)&0x7;
if(DISS) fprintf(stderr,"sbc r%u,r%un",rd,rm);
ra=read_register(rd);
rb=read_register(rm);
rc=ra-rb;
if(!(cpsr&CPSR_C)) rc--;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
if(cpsr&CPSR_C)
{
do_cflag(ra,~rb,1);
do_vflag(ra,~rb,1);
}
else
{
do_cflag(ra,~rb,0);
do_vflag(ra,~rb,0);
}
return(0);
}
//ADC
if((inst&0xFFC0)==0x4140)
{
rd=(inst>>0)&0x07;
rm=(inst>>3)&0x07;
if(DISS) fprintf(stderr,"adc r%u,r%un",rd,rm);
ra=read_register(rd);
rb=read_register(rm);
rc=ra+rb;
if(cpsr&CPSR_C) rc++;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
if(cpsr&CPSR_C) { do_cflag(ra,rb,1); do_vflag(ra,rb,1); }
else            { do_cflag(ra,rb,0); do_vflag(ra,rb,0); }
return(0);
}
//ADD(3) three registers
if((inst&0xFE00)==0x1800)
{
rd=(inst>>0)&0x7;
rn=(inst>>3)&0x7;
rm=(inst>>6)&0x7;
if(DISS) fprintf(stderr,"adds r%u,r%u,r%un",rd,rn,rm);
ra=read_register(rn);
rb=read_register(rm);
rc=ra+rb;
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
do_cflag(ra,rb,0);
do_vflag(ra,rb,0);
return(0);
}
//ASR(2) two register
if((inst&0xFFC0)==0x4100)
{
rd=(inst>>0)&0x07;
rs=(inst>>3)&0x07;
if(DISS) fprintf(stderr,"asrs r%u,r%un",rd,rs);
rc=read_register(rd);
rb=read_register(rs);
rb&=0xFF;
if(rb==0)
{
}
else if(rb<32)
{
do_cflag_bit(rc&(1<<(rb-1)));
ra=rc&0x80000000;
rc>>=rb;
if(ra) //asr, sign is shifted in
{
rc|=(~0)<<(32-rb);
}
}
else
{
if(rc&0x80000000)
{
do_cflag_bit(1);
rc=(~0);
}
else
{
do_cflag_bit(0);
rc=0;
}
}
write_register(rd,rc);
do_nflag(rc);
do_zflag(rc);
return(0);
}
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